An address misalignment fault occurs whenever a generated address does not fit the boundary of a selectled word size. The instruction set of Intel 8086, 80286, 80386, 80486 and Pentium microprocessors permits data access to any byte of memory. These microprocessors employ varying word sizes from 8 bits to 64 bits. It is known that references to misaligned addresses entail a performance penalty because some misaligned address references require two memory accesses. However, the later generations of these microprocessors retain the capability to generate and employ misaligned addresses to maintain compatibility with a large body of existing programs. Instruction set compatibility is a very important market factor for the personal computers employing these microprocessors.
A number of other microprocessors do not permit generation of misaligned addresses. Most particularly microprocessors in the RISC (Reduced Instruction Set Computer) class prohibit misaligned address generation. The regularized instruction set and memory accesses common to RISC microprocessors provide many advantages in speed of operation and processing power over the Intel microprocessors employed in most personal computers. To date this theoretical additional computational power of RISC microprocessors has not overcome the overwhelmingly larger base of application programs available for Intel microprocessors. Consequently, RISC microprocessors have found little success in mainstream general purpose personal computers.
It would be desirable in some applications employing Intel microprocessors to permit address misalignment fault generation. Certain AI (Artificial Intelligence) programs employ data typing within the generated address. If address misalignment faults could be selectively generated, then the least significant address bits could be employed to specify these data types. Upon address misalignment fault generation, a fault recovery program, more typically called an interrupt service routine, would access the word aligned address by masking the least significant bits of the address. At the same time the interrupt service routine would signal interrupted program of the data type for proper handling based upon these least significant bits indicating the data type. This technique, which is very useful in AI programs, permits run time specification of data types.
The prior art represented by U.S. Pat. No. 5,201,043 entitled "SYSTEM USING BOTH A SUPERVISOR LEVEL CONTROL BIT AND USER LEVEL CONTROL BIT TO ENABLE/DISABLE MEMORY REFERENCE ALIGNMENT CHECKING" employs a microprocessor based computer system having multiple privilege levels. The operating system has a high privilege level and has control over whether address misalignment fault generation is allowed. The application program has a low privilege level and has control over whether address misalignment fault generation is requested. The operating system stores individual bits in a control register CR0. In accordance with the Intel microprocessor architecture bit eighteen of this control register CR0 stores an alignment masking bit (AM) that allows or disallows address alignment fault detection. The application program stores individual bits in a flags register EFLAGS. In accordance with the Intel microprocessor architecture bit eighteen of the EFLAGS register stores an alignment check (AC) bit which indicates whether address misalignment fault generation is requested by the application program.